On-chip interconnects and their parasitics are playing increasingly important role in functionality, performance, robustness, and reliability of integrated circuits. Unintended and undesirable effects of parasitic elements lead to post-layout simulations being very different from schematic simulations, and to circuits not reaching their specification requirements.
“Parasitics” or “parasitic elements” generally refer to unintended impedances that degrade electronic circuit performance. The ways in which interconnects of a circuit are laid out and the materials associated with that layout can give rise to unintended resistances, capacitances and inductances that delay signals, induce noise, lead to IR voltage drop and current density (electromigration) violations, cause net and device mismatch, and create other effects that are detrimental to circuit operation. In modern semiconductor technologies, the number of parasitics can be huge, and can exceed the number of design elements (such as transistors) by many orders of magnitude. These parasitics are typically not fully accounted for during initial circuit design, and even when they are, there generally are no optimization tools or methodologies that permit a designer to pinpoint bottlenecks or select an appropriate mitigation or optimization strategy.
What are needed are techniques for addressing these difficulties, that is, for improvements in circuit design tools which provide analysis and visualization of parasitics and facilitate their modification during the circuit design/layout process; ideally, such a design tool would link parasitics to specific physical elements and shapes in the circuit layout and permit a designer to identify and remove/reduce key parasitics as an interactive part of the circuit design/layout process. The present invention satisfies these needs and thus provides an improvement in the functioning of automated or computer-assisted layout and/or analysis tools.
The subject matter defined by the enumerated claims may be better understood by referring to the following detailed description, which should be read in conjunction with the accompanying drawings. This description of one or more particular embodiments, set out below to enable one to build and use various implementations of the technology set forth by the claims, is not intended to limit the enumerated claims, but to exemplify their application. Without limiting the foregoing, this disclosure provides several different examples of techniques that can be used to improve the functioning of automated or computer-assisted circuit design, analysis and/or layout tools, and to speed up effective circuit design and debugging. The various techniques can be embodied as software, in the form of a computer, device, service, cloud service, system or other device or apparatus, in the form of a circuit design or layout file produced or modified as a result of these techniques, or in another manner. While specific examples are presented, the principles described herein may also be applied to other methods, devices and systems as well.